The present invention relates to a method for controlling a plurality of banks included in a semiconductor memory device, and more particularly, to a method for generating signals for controlling each of the plurality of banks employing one control circuit.
In general, a semiconductor memory device is used to store a plurality of data and to provide desired data among the stored data. That is, an operation of the semiconductor memory device is classified into a data write operation for storing data inputted from the exterior and a data read operation for outputting data stored in the semiconductor memory device to the exterior.
Meanwhile, in a typical semiconductor memory device such as a dynamic random access memory (DRAM) device which is a volatile memory device, in order to store data inputted from the exterior in a cell or output data stored in a cell to the exterior, the semiconductor memory device should perform various operations including an active operation, a read/write operation and a precharge operation.
Herein, the active operation and the read/write operation are operations for selecting a certain cell among a plurality of cells included in the semiconductor memory device, and outputting data stored in the certain cell to the exterior or storing data provided from the exterior in the certain cell. Meanwhile, the precharge operation is an operation for making the semiconductor memory device ready for the active operation and the read/write operation.
Therefore, in order to output data stored in the semiconductor memory device to the exterior once or store data from the exterior in the semiconductor memory device once, a time for performing the active operation, the read/write operation and the precharge operation should be secured.
Accordingly, the semiconductor memory device employs a method capable of effectively performing a data input/output operation. That is, the semiconductor memory device includes a plurality of banks obtained by grouping a plurality of cells included in the semiconductor memory device at a certain unit, wherein each bank performs the data input/output operation independently.
FIG. 1 illustrates a block diagram of a conventional semiconductor memory device including a plurality of banks. As shown, the conventional semiconductor memory device includes a plurality of banks BANK0-BANK7, a plurality of bank control blocks BANK0_CONTROL-BANK7_CONTROL, and a bank operation mode signal generating block 100.
The plurality of banks BANK0-BANK7 each performs various operations in response to a corresponding one of a plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N>. The plurality of bank control blocks BANK0_CONTROL-BANK7_CONTROL generates the plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> each of which has a plurality of enable periods that are sequential in response to a plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7>. The bank operation mode signal generating block 100 generates the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> in response to an active command ACT_CMD, a precharge command PCG_CMD and a bank address BANK_ADDR<0:7>.
Under a condition where the active operation should be performed in response to the enabled active command ACT_CMD, the bank operation mode signal generating block 100 selects one of the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> corresponding to the bank address BANK_ADDR<0:7>. The bank operation mode signal generating block 100 enables the selected bank operation mode signal while not enabling the unselected bank operation mode signals. Likewise, in response to the enabled precharge command PCG_CMD, the bank operation mode signal generating block 100 selects one of the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> corresponding to the bank address BANK_ADDR<0:7>. The bank operation mode signal generating block 100 disables the selected bank operation mode signal while not disabling the unselected bank operation mode signals.
The bank control blocks BANK0_CONTROL-BANK7_CONTROL generates the bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> in response to the enabled bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7>, respectively. The bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> have a plurality of sequential enable periods to perform the active operation in the plurality of banks BANK0-BANK7. Likewise, in response to the disabled bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7>, the bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> are generated to perform the precharge operation in the plurality of banks BANK0-BANK7.
FIGS. 2A and 2B illustrate detailed circuit diagrams of the bank operation mode signal generating block and the plurality of bank control blocks described in FIG. 1, respectively.
Referring to FIG. 2A, in response to the active command ACT_CMD and the bank address BANK_ADDR<0:7>, the bank operation mode signal generating block 100 provides a supply voltage VDD to nodes through which the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are outputted, thereby enabling the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> to a logic high level.
Likewise, in response to the precharge command PCG_CMD and the bank address BANK_ADDR<0:7>, the bank operation mode signal generating block 100 provides a ground voltage VSS to the nodes through which the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are outputted, thereby disabling the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> to a logic low level.
Referring to FIG. 2B, each of the bank control blocks BANK0_CONTROL-BANK7_CONTROL includes a plurality of delay units 200<0>, 200<1>, . . . , and 200<N>. The bank control blocks BANK0_CONTROL-BANK7_CONTROL serially delay the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> predetermined times, and output the plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N>, respectively. The delay units 200<0>, 200<1>, . . . , and 200<N> properly adjust logic levels of the plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> by changing a decoding method according to whether the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are enabled or disabled.
When the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are enabled to a logic high level, the plurality of banks BANK0-BANK7 should perform the active operation. Accordingly, the delay units 200<0>, 200<1>, . . . , and 200<N> changes the logic levels of the plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> to levels wherein the active operation is performed in the plurality of banks BANK0-BANK7.
Likewise, when the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are disabled to a logic low level, the plurality of banks BANK0-BANK7 should perform the precharge operation. Accordingly, the delay units 200<0>, 200<1>, . . . , and 200<N> changes the logic levels of the plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> to levels wherein the precharge operations performed in the plurality of banks BANK0-BANK7.
As described above, in the circuit for controlling the conventional semiconductor memory device, the bank operation mode signal generating block 100 generates the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> in response to the active command ACT_CMD, the precharge command PCG_CMD and the bank address BANK_ADDR<0:7>, the plurality of bank control blocks BANK0_CONTROL-BANK7_CONTROL generate the plurality of bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> in response to the plurality of bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7>, so that the active operation and the precharge operation are performed in the plurality of banks BANK0-BANK7.
At this time, the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are just enabled in response to the enabled active command ACT_CMD and disabled in response to the enabled precharge command PCG_CMD. Therefore, although the bank operation mode signals ACT_PCG_CONT<0>-ACT_PCG_CONT<7> are enabled or disabled, the active operation and the precharge operation are not automatically performed in the plurality of banks BANK0-BANK7.
That is, the bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> are used to perform the active operation and the precharge operation in the banks BANK0-BANK7. Since they are generated in the bank control blocks BANK0_CONTROL-BANK7_CONTROL, respectively, various circuits for making the active operation and the precharge operation performed at exact timing in the banks BANK0-BANK7 should be included in each of the bank control blocks BANK0_CONTROL-BANK7_CONTROL. Herein, the various circuits make various operations, such as an operation for disabling a bit line equalizing signal BLEQ, an operation for activating a word line, an operation for activating a bit line sense amplifier (BLSA) and so on, performed sequentially at exact timing,
Therefore, each of the bank control blocks BANK0_CONTROL-BANK7—CONTROL has to include the plurality of delay units 200<0>, 200<1>, . . . , and 200<N> for defining the timing of the above various operations included in the active operation and the precharge operation as illustrated in FIG. 2B.
However, the plurality of delay units 200<0>, 200<1>, . . . , and 200<N> included in each of the bank control blocks BANK0_CONTROL-BANK7_CONTROL occupy a relatively large area compared to a general logic circuit. Therefore, when the semiconductor memory device includes a lot of delay units, it is difficult to reduce a whole size of the semiconductor memory device.
In a memory structure such as the above described conventional semiconductor memory device including the plurality of delay units 200<0>, 200<1>, . . . , and 200<N> in each of the plurality of bank control blocks BANK0_CONTROL-BANK7_CONTROL, the whole size of the semiconductor memory device may be increased according to the number of banks included in the semiconductor memory device. Although the number of banks included in the semiconductor memory device is small, the plurality of delay units may always occupy a certain area of the semiconductor memory device and thus it is difficult to reduce the whole size of the semiconductor memory device.
Further, since the bank operation control signals BANK0_CONT<0:N>-BANK7_CONT<0:N> are generated through different delay units for the banks BANK0-BANK7, the banks BANK0-BANK7 may have minute differences in the timing where the active operation and the precharge operation are performed by banks.